Chiplet Packaging — Final Presentation

Overview

A final presentation for CHE 518 (Fundamentals of Semiconductor Packaging) proposing a machine-learning-accelerated workflow for signal integrity (SI) analysis in chiplet-based advanced packages. It surveys the SI challenges of chiplet architectures (frequency-dependent loss, crosstalk, reflections, TSV/interposer effects, power-delivery noise) and proposes training ML surrogate models on full electromagnetic (EM) simulation data to predict SI metrics far faster than full EM solves. The deliverable is a 15-slide technical presentation including a UCIe channel case study. **Highlight:** ML surrogate models claimed 100-1000x speedup per evaluation vs full EM simulation

Key Achievements

• Designed a four-stage AI-accelerated SI workflow: design-space definition, DOE-based intelligent sampling, ML surrogate training/validation, and rapid optimization with targeted EM verification
• Compared three modeling approaches (full EM, traditional RC extraction, and ML surrogate models) with their accuracy, capacity, and runtime trade-offs, recommending a hybrid ML-plus-EM strategy
• Presented a worked UCIe 24 GT/s die-to-die channel case study: 50 design variants sampled, full 3D EM run, neural network trained to 94% validation accuracy, then 10,000 candidates evaluated in 5 minutes
• Documented technical and adoption challenges (data scarcity/cold-start, ML generalization limits, EDA toolchain integration, standardization gaps) and outlined future directions including on-device LLM design interfaces and SI-PI-thermal co-optimization

Approach

The work frames signal integrity as the key bottleneck in chiplet packaging and argues that ML surrogate models, trained on validated EM simulation data, can predict VTF loss, crosstalk, and eye diagrams in seconds rather than days. Design of Experiments (Latin hypercube, orthogonal arrays, adaptive sampling) is used to sample the parameter space efficiently, neural networks and Gaussian processes serve as surrogates, and full EM simulation is reserved for validating optimized designs. The presentation is grounded in cited industry sources (SemiEngineering, Keysight, UCIe Consortium, Open Compute Project).

Tools & Technologies

Gallery

Results

In the presented UCIe channel case study, the ML-optimized design reportedly improved eye height to 48 mV vs a 40 mV target (+20% margin), cut crosstalk ~40%, and reached 25 ps timing margin vs a 20 ps target, with the ML surrogate hitting 94% validation accuracy and 50-100x faster design speed; see docs/CHE518_Final_Presentation_Elsaady.pdf for the full deliverable.